OISC Prototype

The prototype used through-hole components, and was designed with different functions on different boards. Both these approaches were to aid in the debugging process, and allow re-manufacture of a subset of boards if required.

The prototype consisted of a backplane and the following boards for testing the CPU design:

Registers & Arithmetic Logic Unit
Microcode state machine
Static logic decoder

The prototype bus is compatible with the final bus, so ancillary boards could be tested with it, and in turn, allow full testing of the prototype.

The LED status indicator bargraphs were designed as piggy-back boards to allow more room for onboard ICs, along with reusability.

OISC Prototype Learnings

Apart from a few "Why did I connect that to there?" issues in the (ALU) adder, the major issue, which was quite hard to debug, was a configuration of logic gates that caused a logic glitch (race condition/hazard) due to their propagation delays - giving some very small pulses that meant the program counter incremented at high speed occasionally and unexpectedly.

A redesign of the logic gate combinations meant the race condition would not occur, thus resolving the issue.